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Sept. 1995 Edition 2.0a DATA SHEET MB1508 SERIAL INPUT PLL FREQUENCY SYNTHESIZER SERIAL INPUT PLL FREQUENCY SYNTHESIZER ON CHIP 2.5 GHz PRESCALER DESCRIPTION The Fujitsu MB1508 with an on chip 2.5 GHz dual modulus prescaler is a serial input PLL (Phase Locked Loop) frequency synthesizer with pulse swallow function. It is well suited for BS tuner, CATV system, and TV tuner applications. It operates with a supply voltage of 5.0V typ. and dissipates 16mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology. FEATURES * Power supply voltage: VCC = 4.5 to 5.5V * High operating frequency: fIN = 2.5 GHz (PIN = -4dBm) * 2.5 GHz dual modulus prescaler: P = 256/272, 512/528 * Low supply current: ICC = 16mA typ. * Programmable reference divider consisting of: Binary 2-bit programmable reference counter (R = 256, 512, 1024, 2048) * Programmable divider consisting of: Binary 5-bit swallow counter (A = 0 to 31) Binary 12-bit programmable counter (N = 32 to 4095) * Wide operating temperature: -40_C to +85_C * Plastic 20-pin Flat Package (Suffix: --PF) Plastic Package FPT-20P-M01 Pin Assignment (TOP VIEW) FC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LD ABSOLUTE MAXIMUM RATINGS (See NOTE) RatIng Power Supply Voltage Output Voltage Output Current Storage Temperature NOTE: LE fOUT VCC2 Symbol VCC VO IO TSTG Value -0.5 to +7.0 -0.5 to VCC +0.5 10 -55 to +125 Unit V V mA _C Data Clock VCC1 OSCIN OSCOUT GND D01 D02 fIN GND2 fIN BC1 BC2 BC3 BC4 Permanent device damage may occur if the above Absolute Maximum RatIngs are exceeded.Functional operation should be restricted to the condItions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Copyright (c) 1991 by FUJITSU LIMITED MB1508 MB1508 Block Diagram 2 MB1508 PIN DESCRIPTION Pin No. 1 Pin Name FC I/O Description Phase select input pin of the phase detector. This pin involves an internal pull up resistor. When this pin is low, characteristics of the charge pump and phase detector can be reversed. This input also selects fOUT pin output level, either fr or fp. Please see page 6. Load enable input pin. This pin involves a schmitt trigger circuit. When this pin is high, the data stored in the shift register is transferred into the latch. Serial data of binary code input pin. This pin involves a schmitt trigger circuit. Clock input for 24-bit shift register. This pin involves a schmitt trigger circuit. On rising edge of the clock shifts one bit of data into the shift registers. PLL power supply voltage input pin. Oscillator input pin. Oscillator output pin. A crystal is connected between OSCIN pin and OSCOUT pin. PLL ground pin. Charge pump output pins. Phase characteristics can be reversed depending upon FC pin input level. Band switching output pins. (Open-collector output) Output is controlled by a band bit data, individually. BCX--bit = H : BCX output transistor is ON. BCX--bit = L : BCX output transistor is OFF. (X = 1 to 4) Complementary input pin of fin. Please connect to GND through a capacitor. Prescaler ground pin. Prescaler input pin. This signal is AC coupled. Prescaler power supply voltage input pin. Monitor pin of the phase detector input. fOUT pin outputs either of the programmable reference divider output frequency fr or programmable divider output frequency fp depending upon the FC pin input level. I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LE Data Clock VCC1 OSCIN OSCOUT GND1 DO1 DO2 BC4 BC3 BC2 BC1 fin GND2 fin VCC2 I I I -- I O -- O O O O O I -- I -- 19 fOUT O FC Pin H L fout output signal fr fp 20 LD O Phase detector output pin. Normally this pin outputs high. While the phase difference between fr and fp exists, this pin outputs low. 3 MB1508 FUNCTIONAL DESCRIPTIONS DIVIDE RATIO SETTING Divide ratio can be set using the following equation: fvco = [(P x N)+ (16 x A] x fosc / R Output frequency of external voltage controlled oscillator (VCO) fvco: P: Preset divide ratio of an internal dual modulus prescaler (256 or 512) N: Preset divide ratio of binary 12-bit programmable counter (32 to 4095) A: Preset divide ratio of binary 5-bit swallow counter (0 to 31) Reference oscillator frequency fosc: R: Preset divide ratio of reference counter (256, 512, 1024, 2048) SERIAL DATA INPUT On rising edge of clock shifts one bit of the data into the shift register. When the load enable is high, the data stored in the shift register is transferred to the latch. 24 bit of serial data format is shown below. Data Input Flow LSB N 1 0 N 1 2 B C 4 B C 3 MSB B C 2 B C 1 A 1 A 2 A 3 A 4 A 5 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 N 11 S W R 1 R 2 Divide ratio of swallow counter setting bit Divide ratio of programmable counter setting bit Divide ratio of prescaler setting bit Band switch setting bit Divide ratio of reference counter setting bit 5-BIT SWALLOW COUNTER DIVIDE RATIO (A1 to A5) Divide Ratio A 0 1 2 S 31 A 5 0 0 0 S 1 A 4 0 0 0 S 1 A 3 0 0 0 S 1 A 2 0 0 1 S 1 A 1 0 1 0 S 1 12-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (N1 to N12) Divide Ratio 32 33 34 S 4095 N 12 0 0 0 S 1 N 11 0 0 0 S 1 N 10 0 0 0 S 1 N 9 0 0 0 S 1 N 8 0 0 0 S 1 N 7 0 0 0 S 1 N 6 1 1 1 S 1 N 5 0 0 0 S 1 N 4 0 0 0 S 1 N 3 0 0 0 S 1 N 2 0 0 1 S 1 N 1 0 1 0 S 1 4 MB1508 FUNCTIONAL DESCRIPTIONS REFERENCE COUNTER DIVIDE RATIO (R1 to R2) Divide Ratio R 256 512 1024 2048 R 2 o 0 1 1 R 1 o 1 0 1 Prescaler divide ratio (SW) When divide ratio of prescaler setting bit is high, divide ratio of 256/272 is selected. When divide ratio of prescaler setting bit is low, divide ratio of 512/528 is selected. Band Switch Setting (BC1 to BC4) When band switch setting bit is high, output is ON. When band switch setting bit is low, output is OFF. 5 MB1508 Serial Data Input Timing Data S18 = MSB (SW) (1) Clock S17 (S14) S10 (S8) S9 (S7) S1 = LSB (S1) C: Control bit (C: Control bit) LE t1 t2 t3 t5 t4 1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected. Note: One bit of data is shifted into the shift register on the rising edge of the clock. NOTES: On rising edge of the clock shifts one bit of data into the shift register. When LE is high, the data stored in the shift register is transferred into the latch. PHASE DETECTOR CHARACTERISTICS FC pin selects the phase of the phase detector. Phase characteristics (charge pump output) can be reversed depending upon the FC pin input level. Monitor pin (fOUT) output level is selected by FC pin input level as well . FC=H or open Do1, Do2 fr > fp fr = fp fr < fp Note: H L Z FC=L DO, D02 L Z H fOUT Outputs programmable p reference divider output frequency fr. fOUT Outputs programmable p divider output frequency fp. Z = (High impedance) 1 VCO output frequency VCO CHARACTERISTICS Depending upon VCO polarity, FC pin should be set accordingly: -- When VCO polarity are like FC should be set High or open. 2 -- When VCO polarity are like FC should be set Low. LPF input voltage 6 MB1508 PHASE DETECTOR WAVEFORM fr fp (FC =H) D01, D02 H Z L (FC -L) D01, D02 Z fr > fp fr = fp fr < fp fr < fp fr < fp NOTES: Phase difference detection range: -2 to +2 Spike shape depends on charge pump characteristics. The spike is output to diminish dead band. RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Input Voltage Operating Temperature Symbol VCC VI TA Value Min 4.5 GND -40 Typ 5.0 -- -- Max 5.5 VCC +85 Unit V V _C Handling Precautions * This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices. 7 MB1508 ELECTRICAL CHARACTERISTICS Parameter Power Supply Current Operating Frequency fin OSCIN Symbol ICC fin fOSC Condition Note 1 Note2 -- 2300 to 2500MHz Min -- 10 -- -4 -7 -10 0.5 VCCx 0.7+0.4 -- -- -- -- -- 4.4 Typ 16.0 -- 4 -- -- -- -- -- -- 1.0 -1.0 -60 +50 -- -- -- -- -- -- Max -- 2500 Unit mA MHz 10 6 6 6 -- -- V VCCx0.3-0.4 -- -- -- -- -- V 0.4 1.1 -- mA -- 12 V A A VPP dBm Input Sensitivity fin Pfin 1900 to 2300MHz 10 to 1900MHz OSCIN High-level Input Voltage Low-level Input Voltage High-level Input Current Low-level Input Current FC Input Current High-level Output Voltage Low-level Output Voltage High Impedance Cutoff Current High-level Output Current Low-level Output Current Withstand Output Voltage NOTE: OSCIN Except DO p and BC1 to BC4 DO1, D02 BC1 to BC4 Except DO p and BC1 to BC4 BC1 to BC4 Except fin and OSCIN Data Clock LE VOSC VIH VIL IIH IIL IILFC IOSC VOH VOL IOFF IOH IOL VB -- -- -- -- -- -- -- VCC = 5 0 V 5.0 -- -- -1.0 1.0 -- -- -- -- -- 1: f in = 2.5GHz, OSCIN=4.0MHz, Vcc=5.0V. Inputs are grounded and outputs are open. 2: AC coupling. Minimum operating frequency is measured with a capacitor 1000pF. 8 MB1508 TEST CIRCUIT Prescaler Input Sensitivity 1000 p 0.1 1000 p P*G 50 20 19 18 17 16 15 14 13 12 11 MB1508 1 2 3 4 5 6 7 8 9 10 0.1 9 MB1508 MB1508 APPLICATION CIRCUIT 10 MB1508 PACKAGE DIMENSIONS 20-Lead Plastic Flat Package (Case No.: FPT-20P-M01) .089(2.25) MAX (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT) +.010 +0.25 .500 (12.70 ) -.008 -0.20 .307.016 (7.800.40) INDEX .209.012 (5.300.30) +.016 +0.40 .268 (6.80 ) -.008 -0.20 .020.008 (0.500.20) .018.004 (0.450.10) .005(0.13) M +.002 +0.05 .006 (0.15 ) -.001 -0.02 Details of "A" part "A" .008(0.20) .004(0.10) .450(11.43) REF .020(0.50) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters) (c)1991 FUJITSU LIMITED F20003S-5C 11 MB1508 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. 12 MB1508 FUJITSU LIMITED For further information, please contact: Japan FUJITSU LIMITED Semiconductor Marketing Furukawa Sogo Bldg. 6-1, Marunouchi 2-chome Chiyoda-ku, Tokyo 100 Japan Tel: (03) 3216-3211 Telex: 781-2224361 FAX: (03) 3216-9771 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804 USA Tel: (408) 922-9000 FAX: (408) 432-9044 Europe FUJITSU MIKROELEKTRONIK GmbH Arabella Centre 9.OG Lyoner Strasse 44-48 D-6000 Frankfurt 71 F.R. Germany Tel: (069) 66320 Telex: 411963 FAX: (069) 6632122 Asia FUJITSU MICROELECTRONICS ASIA PTE LIMITED 51 Bras Basah Road Plaza by the Park #06-04/07 Singapore 0718 Tel: 336-1600 Telex: 55373 FAX: 336-1609 (c) 1991 FUJITSU LIMITED IC-07229-2-91-DS 13 |
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